GE Fanuc IS220PAICH1B Mark VIe The Analog Input/Output (PAIC) Module

IS220PAICH1B Functional Description

     The Analog Input/Output (PAIC) pack provides the electrical interface between one or two I/O Ethernet networks and an analog input terminal board. 

     The pack contains a processor board common to all Mark* VIe distributed I/O packs and an acquisition board specific to the analog input function. 

     The pack is capable of handling up to 10 analog inputs, the first eight of which can be configured as ±5 V or ±10 V inputs, or 0-20 mA current loop inputs. The last two inputs may be configured as ±1 mA or 0-20 mA current inputs. 

     The load terminal resistors for current loop inputs are located on the terminal board and voltage is sensed across these resistors by the PAIC. The PAICH1 also includes support for two 0-20 mA current loop outputs. 

    The PAICH2 includes extra hardware to support 0-200 mA current on the first output. 

     Input to the pack is through dual RJ45 Ethernet connectors and a three-pin power input. Output is through a DC-37 pin connector that connects directly with the associated terminal board connector. Visual diagnostics are provided through indicator LEDs, and local diagnostic serial communications are possible through an infrared port. 

     PAICH1A is compatible with the analog input terminal board (TBAIHIC), and the STAI board, but not the DIN rail-mounted DTAI board. The following table gives details of the compatibility: 

     For this reason, the PAIC is only compatible with the H1C version of TBAI and will report a board compatibility problem with any of the earlier revisions. No physical damage will result if a PAIC is powered up on an older board in error.

1 Securely mount the desired terminal board. 

2 Directly plug one PAIC I/O pack for simplex or three PAIC I/O packs for TMR into the terminal board connectors. 

3 Mechanically secure the packs using the threaded studs adjacent to the Ethernet ports. The studs slide into a mounting bracket specific to the terminal board type. The bracket location should be adjusted such that there is no right-angle force applied to the DC-37 pin connector between the pack and the terminal board. The adjustment should only be required once in the life of the product. 

4 Plug in one or two Ethernet cables depending on the system configuration. The pack will operate over either port. If dual connections are used, the standard practice is to connect ENET1 to the network associated with the R controller. 

5 Apply power to the pack by plugging in the connector on the side of the pack. It is not necessary to insert this connector with the power removed from the cable as the I/O pack has inherent soft-start capability that controls current inrush on power application. 

6 Configure the I/O pack as necessary.  

The processor board in the pack is common to all Mark VIe Ethernet I/O packs. It contains the following: 

• High-speed processor with RAM and flash memory 

• Two fully independent 10/100 Ethernet ports with connectors 

• Hardware watchdog timer and reset circuit 

• Internal I/O pack temperature sensor 

• Infrared serial communications port 

• Status-indication LEDs 

• Electronic ID and the ability to read IDs on other boards 

• Substantial programmable logic supporting the acquisition board 

• Input power connector with soft start/current limiter 

• Local power supplies, including sequencing and monitoring 

The following I/O pack and terminal board combinations are approved for use in hazardous locations

• Mark VIe Analog I/O pack IS220PAICH1A with terminal boards (accessories) IS200STAIH1A, IS200STAIH2A, or IS200TBAIH1C 

• Mark VIe Analog I/O pack IS220PAICH1B with terminal boards (accessories) IS200STAIH1A, IS200STAIH2A, or IS200TBAIH1C 

• Mark VIeS Safety Analog I/O pack IS220YAICS1A with terminal boards (accessories) IS200STAIS1A, IS400STAIS1A, IS200STAIS2A, IS400STAIS2A, IS200TBAIS1C, or IS400TBAIS1C 

• Mark VIeS Safety Analog I/O pack ISx2yYAICS1B (where x = 2 or 4 and y = 0 or 1) with terminal boards (accessories) ISx0ySTAIS1A, ISx0ySTAIS2A, or ISx0yTBAIS1C

Ms Josslyn Yin

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